DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 240

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–26
Figure 6–24. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Data
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
TCCS
Figure 6–24
You must calculate the RSKM value to decide whether or not data can be sampled
properly by the LVDS receiver with the given data rate and device. A positive RSKM
value indicates that the LVDS receiver can sample the data properly, whereas a
negative RSKM indicates that it cannot.
shows the relationship between the RSKM, TCCS, and the receiver’s SW.
TCCS
RSKM
RSKM
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Time Unit Interval (TUI)
Clock Placement
Falling Edge
SW
Internal
TUI
SW
Clock
RSKM
RSKM
TCCS
Source-Synchronous Timing Budget
May 2011 Altera Corporation
TCCS
2