DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 35

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Electrical Characteristics
Table 2–8. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices—Preliminary
May 2011 Altera Corporation
25- R
25- R
25- R
50- R
50- R
50- R
100- R
Note to
(1) Pending silicon characterization.
Symbol
Table
S
S
S
S
S
S
D
2–8:
Calibration accuracy for the calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change.
without calibration resistance tolerance to PVT changes.
Internal series termination
without calibration (25-
setting)
Internal series termination
without calibration (25-
setting)
Internal series termination
without calibration (25-
setting)
Internal series termination
without calibration (50-
setting)
Internal series termination
without calibration (50-
setting)
Internal series termination
without calibration (50-
setting)
Internal differential
termination (100- setting)
Description
V
V
V
V
CCIO
CCIO
CCIO
CCIO
V
V
V
Conditions
CCIO
CCIO
CCIO
= 3.0 and 2.5 V
= 1.8 and 1.5 V
= 3.0 and 2.5 V
= 1.8 and 1.5 V
= 1.2 V
= 1.2 V
= 2.5 V
Stratix V Device Handbook Volume 1: Overview and Datasheet
Table 2–8
±30
±30
±35
±30
±30
±35
±25
C2
Resistance Tolerance
lists the Stratix V OCT
C3,I3
±40
±40
±50
±40
±40
±50
±25
C4,I4
±40
±40
±50
±40
±40
±50
±25
(Note 1)
Unit
%
%
%
%
%
%
%
2–7