DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 423

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
1
Figure 2–6. ×1 Clock Lines Used for Non-Bonded Configuration
Notes to
(1) Stratix V devices 5SGXB5, 5SGXB6, 5SGSB7, and 5SGSB8 have one transceiver bank on each side with only three
(2) You can use the central clock divider as a local clock divider.
The ×6 and ×N clock lines are used for bonded configurations and route both the
serial clock and parallel clock from the central clock dividers to the transceiver
channels.
The ×6 and ×N clock lines can be used to route the serial clock from the central clock
dividers to the transceiver channels for non-bonded configurations to conserve the
number of transmit PLLs used in the design.
Transceiver Bank
Transceiver Bank
transceiver channels. For more information, refer to the
Figure
2–6:
(1)
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Central Clock
Central Clock
Central Clock
Local Clock
Local Clock
Local Clock
Local Clock
Local Clock
Local Clock
Divider (2)
Divider (2)
Divider (2)
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
Divider
Divider
Divider
Divider
Divider
Divider
Serial Clock
Serial Clock
Serial Clock
Transceiver Architecture in Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
×1 Clock Lines
chapter.
ATX PLL
ATX PLL
ATX PLL
2–7