DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 260

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–16
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
When using static phase offset, you can specify the phase offset amount in the
UniPHY megafunction as a positive number for addition or a negative number for
subtraction. You can also have a dynamic phase offset that is always added to,
subtracted from, or both added to and subtracted from the DLL phase shift. When
you add or subtract, you can dynamically input the phase offset amount into the
offset[6..0] port. When you want to both add and subtract dynamically, you
control the addnsub signal in addition to the offset[6..0] signals. The phase offset is
not PVT-compensated.
Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
May 2011 Altera Corporation