DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 195

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
OCT Support and I/O Termination Schemes
Figure 5–6. Dynamic R
May 2011 Altera Corporation
50 Ω
50 Ω
Transmitter
Receiver
Dynamic OCT
Stratix V devices support dynamic R
banks.
Dynamic R
disabled when it acts as a driver. Similarly, dynamic R
bidirectional I/O acts as a driver and is disabled when it acts as a receiver. This
feature is useful for terminating any high-performance bidirectional path because
signal integrity is optimized depending on the direction of the data.
Altera recommends using the new I/O standards for the DDR3 memory interface
with dynamic OCT schemes. These I/O standards save board space by reducing the
number of external termination resistors used.
Using dynamic OCT also helps save power because device termination is internal
instead of external. Termination only switches on during input operation, thus
drawing less static power.
T
OCT in Stratix V Devices
Stratix V OCT
Stratix V OCT
Figure 5–6
T
V
V
GND
GND
OCT is enabled only when the bidirectional I/O acts as a receiver and is
CCIO
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
shows the termination schemes supported in Stratix V devices.
Z
Z
0
0
= 50 Ω
= 50 Ω
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
S
and R
T
V
V
GND
GND
OCT for bidirectional I/Os in all I/O
CCIO
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
Stratix V OCT
Stratix V OCT
S
OCT is enabled only when the
Transmitter
Receiver
50 Ω
50 Ω
5–19