DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 143

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Clock Networks in Stratix V Devices
Figure 4–2. RCLK Networks
May 2011 Altera Corporation
Regional Clock Networks
Periphery Clock Networks
RCLK networks only pertain to the quadrant they drive into. RCLK networks provide
the lowest clock delay and skew for logic contained within a single device quadrant.
The Stratix V device IOEs and internal logic within a given quadrant can also drive
RCLKs to create internally generated regional clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 4–2
The PCLK networks shown in
collections of individual clock networks driven from the periphery of the Stratix V
device. Depending on the routing direction, there are vertical PCLKs from the top and
bottom periphery and horizontal PCLKs from the left and right periphery. Clock
outputs from the dynamic phase aligner (DPA) block, programmable logic device
(PLD)-transceiver interface clocks, I/O pins, and internal logic can drive the PCLK
networks.
PCLKs have higher skew when compared with GCLK and RCLK networks. You can
use PCLKs for general purpose routing to drive signals into and out of the Stratix V
device.
RCLK[45..40]
RCLK[70..64]
RCLK[91..85]
RCLK[63..58]
shows the RCLK networks in Stratix V devices.
RCLK[39..30]
RCLK[9..0]
Q1
Q4
Figure 4–3
Q2
Q3
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
RCLK[19..10]
RCLK[29..20]
through
RCLK[51..46]
RCLK[84..78]
RCLK[57..52]
RCLK[77..71]
Figure 4–6 on page 4–5
are
4–3