DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 503

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV52006-1.2
10G Low Latency Configuration
Figure 5–1. 10G Low Latency Datapath
Stratix V Device Handbook Volume 3: Transceivers
May 2011
May 2011
SV52006-1.2
tx_coreclk
tx_clkout
rx_coreclk
rx_clkout
Fabric
FPGA
CMU PLL
(From the ×1 Clock Lines)
This chapter describes the custom transceiver configuration datapath in Stratix
devices for the 10G and standard physical coding sublayer (PCS) blocks.
This chapter contains the following sections:
■
■
A Low Latency PHY IP core using the 10G PCS is available for 32-bit, 40-bit, 50-bit,
64-bit, or 66-bit PCS data width configurations.
Latency configuration datapath.
Serial Clock
“10G Low Latency Configuration”
“Standard PCS Custom and Low Latency Configurations” on page 5–8
Central/ Local Clock Divider
BER
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
5. Transceiver Custom Configurations in
Clock Divider
Parallel and Serial Clocks
(Only from the Central Clock Divider)
Figure 5–1
Transmitter 10G PCS
Receiver 10G PCS
Stratix V Devices
shows the 10G Low
Parallel Clock
Serial Clock
Parallel and Serial Clock
Transmitter PMA
PMA Receiver
®
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