DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 440

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–24
Figure 2–17. Transmitter Datapath Interface Clocking
Stratix V Device Handbook Volume 3: Transceivers
f
1
(Quartus II Selected Clock)
(User Selected Clock)
FPGA Fabric
tx_coreclkin
tx_clkout
All configurations using the standard PCS channel must have a 0 parts per million
(PPM) difference between the transmitter datapath interface clock and the read side
clock of the TX phase compensation FIFO.
For more information about interface clocking for each configuration, refer to the
Transceiver Custom Configurations in Stratix V Devices
for each configuration in the
chapter.
You can clock the transmitter datapath interface by using one of the following:
■
■
User-selection is provided to share the transceiver datapath interface clocks to reduce
GCLK, RCLK, and PCLK resource utilization in your design.
Quartus II-selected transmitter datapath interface clock
User-selected transmitter datapath interface clock
tx_clkout
Transmitter Data
Transmitter Data
Transceiver Protocol Configurations in Stratix V Devices
Compensation
Phase
FIFO
FIFO
TX
TX
Chapter 2: Transceiver Clocking in Stratix V Devices
Parallel Clock
chapter and the clocking sections
Parallel Clock
FPGA Fabric-Transceiver Interface Clocking
Transmitter Standard PCS
Transmitter Data
Transmitter Data
Transmitter 10G PCS
May 2011 Altera Corporation