DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 166

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–26
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Clock Feedback Modes
1
Stratix V PLLs support up to six different clock feedback modes. Each mode allows
clock multiplication and division, phase shifting, and programmable duty cycle.
The input and output delays are fully compensated by a PLL only when using the
dedicated clock input pins associated with a given PLL as the clock source. When a
RCLK or GCLK network drives the PLL or the PLL is driven by a dedicated clock pin
that is not associated with the PLL, the input and output delays may not be fully
compensated in the Quartus II software. An example is when you configure a PLL in
zero-delay buffer mode and the PLL input is driven by an associated dedicated clock
input pin. In this configuration, a fully compensated clock path results in zero delay
between the clock input and one of the output clocks from the PLL. However, if the
PLL input is instead fed by a non-dedicated input (using the GCLK network), the
output clock may not be perfectly aligned with the input clock. Refer to
on page 4–19
to their associated PLLs.
Source Synchronous Mode
If the data and clock arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input register.
Figure 4–21
recommends source synchronous mode for source-synchronous data transfers. Data
and clock signals at the IOE experience similar buffer delays as long as you use the
same I/O standard.
Figure 4–21. Phase Relationship Between Clock and Data in Source Synchronous Mode
Source synchronous mode compensates for the delay of the clock network used plus
any difference in the delay between these two paths:
■
■
Data pin to the IOE register input
Clock input pin to the PLL PFD input
shows an example waveform of the clock and data in this mode. Altera
through
Clock at the register
Data at the register
reference clock
at the input pin
Figure 4–18 on page 4–22
Data pin
PLL
Chapter 4: Clock Networks and PLLs in Stratix V Devices
for a mapping of dedicated clock pins
May 2011 Altera Corporation
Figure 4–15
Stratix V PLLs