DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 16

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–10
Low-Power Serial Transceivers
Figure 1–1. Stratix V GT/GX/GS Device Chip View
Notes to
(1) This figure represents a given variant of a Stratix V device with transceivers. Other variants may have a different floorplan than the one shown here.
(2) You can use the unused transceiver channels as additional transceiver transmit PLLs.
Stratix V Device Handbook
Figure
1–1:
Stratix V FPGAs deliver the industry’s most flexible transceivers with the highest
bandwidth from 600 Mbps to 28 Gbps, low bit error ratio (BER), and low power.
Stratix V transceivers have many enhancements to improve flexibility and robustness.
These enhancements include robust analog receive clock and data recovery (CDR),
advanced pre-emphasis, and equalization for 14.1 Gbps backplanes. In addition, all
transceivers are identical with the full featured embedded PCS hard IP to simplify the
design, lower the power, and save valuable core resources.
Stratix V transceivers are designed to be compliant with a wide range of standard
protocols and data rates, and are equipped with a variety of signal-conditioning
features to support backplane, optical module, and chip-to-chip applications.
Stratix V transceivers are located on the left and right sides of the device, as shown in
Figure
from coupling into the transceivers, thereby ensuring optimal signal integrity. The
transceiver channels consist of the physical medium attachment (PMA), PCS, and
high-speed clock networks. You can also use the unused transceiver PMA channels as
additional transmit PLLs.
1–1. They are isolated from the rest of the chip to prevent core and I/O noise
I/O, LVDS, and Memory Interface
I/O, LVDS, and Memory Interface
Core Logic
Fabric
Core Logic
Fabric
(Note 1)
Table 1–6
lists the transceiver PMA features.
Chapter 1: Stratix V Device Family Overview
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS
June 2011 Altera Corporation
Low-Power Serial Transceivers
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
PMA
PMA
PMA
PMA
PMA
(2)