DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 23

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
Power Management
Power Management
Incremental Compilation
Enhanced Configuration and Configuration via Protocol
June 2011 Altera Corporation
Stratix V devices leverage FPGA architectural features and process technology
advancements to reduce total power consumption by as much as 30% when
compared with Stratix IV devices at the same performance level.
Stratix V devices continue to provide Programmable Power Technology, introduced in
earlier generations of Stratix FPGA families. The Quartus II software PowerPlay
feature identifies critical timing paths in a design and biases core logic in that path for
high performance. The PowerPlay feature also identifies non-critical timing paths and
biases core logic in that path for low power instead of high performance. PowerPlay
automatically biases core logic to meet performance and optimize power
consumption.
Additionally, Stratix V devices have a number of hard IP blocks that not only reduce
logic resources but also deliver substantial power savings compared to soft
implementations. The list includes PCIe Gen1/Gen2/Gen3, 10G/40G/100G Ethernet,
Interlaken PCS, hard I/O FIFOs, and transceivers. Hard IP blocks consume up to 50%
less power than equivalent soft implementations.
Stratix V transceivers are also designed for power efficiency. As a result, the
transceiver channels consume 50% less power than the previous generation of Stratix
FPGAs. The transceiver PMA consumes approximately 90 mW at 6.5 Gbps and
170 mW at 12.5 Gbps.
The Quartus II software incremental compilation feature reduces compilation time by
up to 70% and preserves performance to ease timing closure. Incremental compilation
supports top-down, bottom-up, and team-based design flows. The incremental
compilation feature facilitates modular hierarchical and team-based design flows
where different designers compile their respective sections of a design in parallel.
Furthermore, different designers or IP providers can develop and optimize different
blocks of the design independently, which you can then import into the top-level
project.
Stratix V device configuration is enhanced for ease-of-use, speed, and cost. Stratix V
devices support a new 4-bit bus Active Serial mode (AS×4). AS×4 supports up to a
400 Mbps data rate using small low-cost quad interface Flash devices. This new mode
is easy to use and offers an ideal balance between cost and speed. Finally, the Fast
Passive Parallel (FPP) interface is enhanced to support 8-, 16-, and 32-bit data widths
to meet a wide range of performance and cost goals.
You can configure Stratix V FPGAs using Configuration via Protocol (CvP) with PCIe.
CvP with PCIe separates the configuration process into two parts: the PCIe hard IP
and periphery and the core logic fabric. CvP uses a much smaller amount of external
memory (flash or ROM) because it only has to store the configuration file for the PCIe
hard IP and periphery. Also, the 100 ms power-up to active time (for PCIe) is much
Stratix V Device Handbook
1–17