DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 272

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–28
Table 7–8. DQS Configuration Block Bit Sequence (Part 2 of 2)
Document Revision History
Table 7–9. Document Revision History
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
52
53
54
55..56
57
58
59..60
61..62
63
64
65
66..68
69
70..77
78..85
86
87..88
89
90
91..93
94..96
97
98
99
100
May 2011
December 2010
July 2010
Date
Bit
Table 7–9
Version
1.2
1.1
1.0
lists the revision history for this chapter.
■
■
■
■
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
Chapter moved to volume 2 for the 11.0 release.
Updated
Updated
Minor text edits.
Figure
Table
enaoutputcycledelaysetting[0..2]
postamblezerophasesetting[0..1]
dqoutputzerophasesetting[0..1]
enaoctcycledelaysetting[0..2]
dqsdisablendelaysetting[0..7]
enadqscycledelaysetting[0..2]
ck2xoutputphasesetting[0..1]
enadqsenablephasetransferreg
7–2,
dqsenabledelaysetting[0..7]
7–4,
dividerioehratephaseinvert
dqsinputphasesetting[0..1]
enaoutputphasetransferreg
enainputcycledelaysetting
enainputphasetransferreg
enaoctphasetransferreg
enadqsphasetransferreg
dq2xoutputphaseinvert
ck2xoutputphaseinvert
Table
dq2xoutputpowerdown
ck2xoutputpowerdown
Figure
postamblepowerdown
dividerphaseinvert
7–7, and
Chapter 7: External Memory Interfaces in Stratix V Devices
7–6,
Bit Name
—
—
—
Figure
Changes
Table
7–13,
7–8.
Figure
7–14, and
May 2011 Altera Corporation
Document Revision History
Figure
7–17.