DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 170

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–30
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 4–26
ZDB mode.
Figure 4–26. Phase Relationship Between the PLL Clocks in ZDB Mode
Note to
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
Figure 4–27
(fbin) is phase-aligned with the clock input pin. Aligning these clocks allows you to
remove clock delay and skew between devices. EFB mode is supported on only the
center and corner PLLs in Stratix V devices.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) and becomes part of the feedback loop. Also,
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
When using external feedback mode, you must use the same I/O standard on the
input clock, feedback input, and output clocks. Left and right PLLs support this mode
when using single-ended I/O standards only.
Figure
4–26:
shows an example waveform of the PLL clocks’ phase relationship in
PLL Clock at the
Register Clock Port (1)
shows that in external feedback mode, the external feedback input pin
PLL Reference
Dedicated PLL
Clock Outputs
Clock at the
Input Pin
Phase Aligned
Chapter 4: Clock Networks and PLLs in Stratix V Devices
May 2011 Altera Corporation
Stratix V PLLs