DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 144

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–4
Figure 4–3. PCLK Networks—5SGXA3 and 5SGXA4 Devices
Figure 4–4. PCLK Networks—5SGXB5 and 5SGXB6 Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Legal clock sources for PCLK networks are clock outputs from the DPA block,
PLD-transceiver interface clocks, horizontal I/O pins, and internal logic.
Horizontal
PCLK[50..65]
Horizontal
PCLK[34..49]
Horizontal
PCLK[0..11]
Horizontal
PCLK[12..23]
Horizontal
PCLK[24..35]
Horizontal
PCLK[36..47]
Horizontal
PCLK[0..15]
Horizontal
PCLK[16..33]
Vertical
PCLK[21..41]
Vertical
PCLK[20..39]
Vertical
PCLK[0..20]
Vertical
PCLK[0..19]
Q1
Q4
Q1
Q4
Q2
Q3
Q2
Q3
Chapter 4: Clock Networks and PLLs in Stratix V Devices
Vertical
PCLK[86..105]
Vertical
PCLK[66..85]
Vertical
PCLK[76..95]
Vertical
PCLK[96..115]
Horizontal
PCLK[116..131]
Horizontal
PCLK[84..95]
Horizontal
PCLK[72..83]
Horizontal
PCLK[60..71]
Horizontal
PCLK[48..59]
Horizontal
PCLK[98..115]
Horizontal
PCLK[66..81]
Horizontal
PCLK[82..97]
Clock Networks in Stratix V Devices
May 2011 Altera Corporation