DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 142

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–2
Figure 4–1. GCLK Networks
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Global Clock Networks
f
Stratix V devices have up to 56 dedicated single-ended clock pins or 28 dedicated
differential clock pins (CLK[0..27]p and CLK[0..27]n) that can drive either the GCLK
or RCLK networks.
input pins connectivity to the GCLK and RCLK networks, respectively.
For more information about how to connect the clock input pins, refer to the
Device Family Pin Connection
Stratix V devices provide up to 16 GCLKs that can drive throughout the device,
serving as low-skew clock sources for functional blocks such as adaptive logic
modules (ALMs), digital signal processing (DSP) blocks, embedded memory blocks,
and PLLs. Stratix V device I/O elements (IOEs) and internal logic can also drive
GCLKs to create internally generated global clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 4–1
GCLK[0..3]
shows the GCLK networks in Stratix V devices.
Table 4–2 on page 4–9
GCLK[12..15]
GCLK[4..7]
Q1
Q4
Guidelines.
Q2
Q3
and
Chapter 4: Clock Networks and PLLs in Stratix V Devices
GCLK[8..11]
Table 4–3 on page 4–10
Clock Networks in Stratix V Devices
May 2011 Altera Corporation
list the clock
Stratix V