DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 93

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
Document Revision History
Document Revision History
Table 1–1. Document Revision History
May 2011 Altera Corporation
May 2011
December 2010
July 2010
Date
LAB Power Management Techniques
f
Version
The following techniques are used to manage static and dynamic power consumption
within the LAB:
■
■
■
For more information about implementing static and dynamic power consumption
within the LAB, refer to the
Handbook.
Table 1–1
1.2
1.1
1.0
To save AC power, the Quartus II software forces all adder inputs low when the
ALM adders are not in use.
Stratix V LABs operate in high-performance mode or low-power mode. The
Quartus II software automatically chooses the appropriate mode for the LAB,
based on the design, to optimize speed versus leakage trade-offs.
Clocks represent a significant portion of dynamic power consumption due to their
high switching activity and long paths. The LAB clock that distributes a clock
signal to registers within a LAB is a significant contributor to overall clock power
consumption. Each LAB’s clock and clock enable signals are linked. For example, a
combinational ALUT or register in a particular LAB using the labclk1 signal also
uses the labclkena1 signal. To disable a LAB-wide clock power consumption
without disabling the entire clock tree, use the LAB-wide clock enable to gate the
LAB-wide clock. The Quartus II software automatically promotes register-level
clock enable signals to the LAB-level. All registers within the LAB that share a
common clock and clock enable are controlled by a shared, gated clock. To take
advantage of these clock enables, use a clock-enable construct in your HDL code
for the registered logic.
■
■
■
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
Chapter moved to volume 2 for the 11.0 release.
Updated
Minor text edits.
lists the revision history for this chapter.
Figure
1–6.
Power Optimization
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Changes
chapter in volume 2 of the Quartus II
1–15