DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 133

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
Operational Mode Descriptions
Figure 3–14. One Sum of Two 18 x 18 Multipliers or Two 16 x 16 Multipliers for Stratix V Devices
Notes to
(1) For 18-bit multiplier adder sum mode, the input data width is 18 bits and the output data width is 37 bits.
(2) For 16-bit multiplier adder sum mode, the input data width is 16 bits and the unused input bit requires padding with zeroes. The output data width
May 2011 Altera Corporation
is 33 bits.
SUB_COMPLEX
Figure
Multiplier Adder Sum Mode
datab_0[ ]
dataa_0[ ]
datab_1[ ]
dataa_1[ ]
3–14:
Stratix V devices support two-multiplier adder sum mode and four-multiplier adder
sum mode. For a two-multiplier adder configuration, the Stratix V variable precision
DSP blocks can support 16-bit, 18-bit, 27-bit, and 18 × 36 multipliers. You require two
variable precision DSP blocks to implement 27-bit and 18 x 36 multiplier adder sum
mode. Stratix V devices support one sum of four 18-bit multipliers with two variable
precision DSP blocks.
DSP blocks in the multiplier adder sum mode.
Figure 3–14
Mult_L
Mult_H
x
x
through
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Adder
+/-
Figure 3–17
Chainout adder/
accumulator
+
show the variable precision
(Note
1),
(2)
Result[]
3–17