DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 207

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
Figure 5–17. LVDS I/O Standard Termination
Notes to
(1)
(2) All I/O banks support true LVDS output buffers and emulated LVDS_E_3R I/O standards. The emulated LVDS output buffers are configured with
May 2011 Altera Corporation
For LVDS
the R
two single-ended output buffers and can be tri-stated.
Figure
P
value is 120 .
output with a three-resistor network, the R
5–17:
Three-Resistor
(Single-Ended
OCT Receiver
OCT Receive
LVDS_E_3R)
Termination
Termination
Output with
(True LVDS
On-Board
LVDS
In Stratix V devices, the LVDS I/O standard requires a 2.5-V V
input buffer requires 2.5-V V
resistor between the two signals at the input buffer. Stratix V devices provide an
optional 100-  differential termination resistor in the device using R
V
Figure 5–17
is available in all I/O banks.
Network,
External
Output)
CCIO
(2)
(2)
and V
shows LVDS I/O standard termination. The on-chip differential resistor
Single-Ended Outputs
CCPD
Differential Outputs
Differential Outputs
Transmitter
are set to 2.5 V.
S
(Note 1)
and R
P
values are 120  and 170 , respectively. For LVDS output with one-resistor network,
External Resistor
CCPD
≤
1 inch
R
R
S
S
Joey dear dear
. The LVDS receiver requires a 100-  termination
50 Ω
50 Ω
50 Ω
50 Ω
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
R
P
LVDS
100 Ω
50 Ω
50 Ω
Differential Inputs
Differential Inputs
Differential Inputs
100 Ω
100 Ω
Stratix V OCT
Stratix V OCT
Stratix V OCT
CCIO
level. The LVDS
D
OCT when
5–31