DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 403

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
May 2011 Altera Corporation
Single-Width Mode
Figure 1–25
8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data
word) with proper disparity. If the tx_datak input is high, the 8B/10B encoder
translates the input data[7:0] to a 10-bit control word. If the tx_datak input is low,
the 8B/10B encoder translates the input data[7:0] to a 10-bit data word.
shows the conversion format. The LSB is transmitted first.
Figure 1–26. 8B/10B Conversion Format
Control Code Encoding
The 8B/10B block provides the tx_datak signal to indicate whether the 8-bit data at
the tx_parallel_data signal should be encoded as a control word (Kx.y). When
tx_datak is low, the 8B/10B encoder block encodes the byte at the tx_parallel_data
signal as data (Dx.y). When tx_datak is high, the 8B/10B encoder encodes the input
data as a Kx.y code group.
word (K28.5). The rest of the tx_parallel_data bytes are encoded as a data word
(Dx.y).
Figure 1–27. Control Word and Data Word Transmission
The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters
for which tx_datak must be asserted. If you assert tx_datak for any other set of bytes,
the 8B/10B encoder might encode the output 10-bit code as an invalid code (it does
not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y code, depending on
the value entered. It is possible for a downstream 8B/10B decoder to decode an
invalid control word into a valid Dx.y code without asserting code error flags.
tx_datain[7:0]
code group
tx_datak
clock
shows the 8B/10B encoder in single-width mode. In this mode, the
D3.4
83
H G F E D C B A
7
MSB
j
9
6
D24.3
Figure 1–27
78
h
8
5
g
7
4
8B/10B Conversion
f
6
3
D28.5
BC
i
5
2
shows the second 0xBC encoded as a control
e d c b a
4
1
3
0
K28.5
BC
2
1
Stratix V Device Handbook Volume 3: Transceivers
control_code
D15.0
LSB
0
0F
D0.0
00
D31.5
BF
Figure 1–26
D28.1
3C
1–31