DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 397

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
May 2011 Altera Corporation
1
8B/10B Decoder
PCIe mode requires the serial data sent over the link to be 8B/10B encoded to
maintain the DC balance in the transmitted serial data. This protocol requires the
receiver PCS logic to implement an 8B/10B decoder to decode the data before
forwarding it to the upper layers for packet processing.
The receiver channel PCS datapaths implement the 8B/10B decoder after the rate
match FIFO. In configurations with the rate match FIFO enabled, the 8B/10B decoder
receives data from the rate match FIFO. In configurations with the rate match FIFO
disabled, the 8B/10B decoder receives data from the word aligner.
8B/10B Decoder in Single-Width Mode
Figure 1–18
8B/10B decoder receives 10-bit data from the rate match FIFO or word aligner (when
the rate match FIFO is disabled) and decodes it into an 8-bit data +1-bit control
identifier. The decoded data is fed to the byte deserializer or the receiver phase
compensation FIFO (if byte deserializer is disabled).
Figure 1–18. 8B/10B Decoder in Single-Width Mode
The 8B/10B decoder is designed toward Clause 36 in the IEEE802.3 specification.
The 8B/10B decoder operates in single-width mode in the PCIe configuration only.
PCIe forces selection of the 8B/10B decoder in the receiver datapath.
Control Code Group Detection
The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or
control code group on the rx_datak signal. If the received 10-bit code group is one of
the 12 control code groups (/Kx.y/) specified in the IEEE802.3 specification, the
rx_datak signal is driven high. If the received 10-bit code group is a data code group
(/Dx.y/), the rx_datak signal is driven low.
shows the 8B/10B decoder in single-width mode. In this mode, the
Current Running Disparity
rx_dataout[15:8]
rx_dataout[7:0]
rx_ctrldetect[1]
rx_errdetect[1]
rx_ctrldetect
rx_disperr[1]
rx_errdetect
rx_disperr
Single-Width Mode
8B/10B Decoder
8B/10B Decoder
(LSB Byte)
(LSB Byte)
Stratix V Device Handbook Volume 3: Transceivers
recovered clock or
tx_clkout[0]
recovered clock or
tx_clkout[0]
datain[19:10]
datain[9:0]
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