DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 475

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
May 2011 Altera Corporation
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Transmitter Electrical Idle Generation
The PIPE interface block in Stratix V devices puts the transmitter buffer in the channel
in an electrical idle state when the electrical idle input signal is asserted. During
electrical idle, the transmitter buffer differential and common configuration output
voltage levels are compliant to the PCIe Base Specification 2.0 for both PCIe Gen1 and
Gen2 data rates.
The PCIe specification requires the transmitter buffer to be in electrical idle in certain
power states. For more information about input signal levels required in different
power states, refer to
For more information about the electrical idle input signal and transmitter buffer
state, refer to the PCI Express PIPE PHY IP Core chapter in the
Core User
Power State Management
The PCIe specification defines four power states—P0, P0s, P1, and P2—that the
physical layer device must support to minimize power consumption:
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■
The PIPE interface in Stratix V transceivers provides an input port for each transceiver
channel configured in a PIPE configuration.
For more information about input signals and status signals to manipulate power
states, refer to the PCI Express PIPE PHY IP Core chapter in the
IP Core User
When transitioning from the P0 power state to lower power states (P0s, P1, and P2),
the PCIe specification requires the physical layer device to implement power saving
measures. Stratix V and transceivers do not implement these power saving measures
except putting the transmitter buffer in electrical idle in the lower power states.
8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and
Status State Machine (LTSSM) state machine enters a polling compliance substate.
The polling compliance substate assesses if the transmitter is electrically compliant
with the PCIe voltage and timing specifications.
For more information about the 8B/10B signals required for compliance pattern
transmission support, refer to the PCI Express PIPE PHY IP Core chapter in the
Altera Transceiver PHY IP Core User
Receiver Electrical Idle Inference
The PCIe protocol allows inferring the electrical idle condition at the receiver instead
of detecting the electrical idle condition using analog circuitry.
P0 is the normal operating state during which packet data is transferred on the
PCIe link.
P0s, P1, and P2 are low-power states into which the physical layer must transition
as directed by the PHY-MAC layer to minimize power consumption.
Guide.
Guide.
“Power State
Guide.
Management”.
Stratix V Device Handbook Volume 3: Transceivers
Altera Transceiver PHY IP
Altera Transceiver PHY
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