DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 54

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Figure 2–3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
May 2011 Altera Corporation
0.1 UI
Sinusoidal Jitter Amplitude
P-P
Figure 2–3
for a data rate less than 1.25 Gbps.
DQ Logic Block and Memory Output Clock Jitter Specifications
Table 2–29
Table 2–29. DQS Phase Offset Delay Per Setting for Stratix V Devices—Preliminary
Notes to
(1) These numbers are preliminary pending silicon characterization.
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when
(Note
using a –2 speed grade and applying a 10-phase offset setting to a 90° phase shift at 400 MHz, the expected
average cumulative delay is [625 ps + (10 × 10 ps) ± 20 ps] = 725 ps ± 20 ps.
1), (2),
Table
Speed Grade
shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification
lists the DQS phase offset delay per stage for Stratix V devices.
2–29:
(3)
–2
–3
–4
20db/dec
baud/1667
Min
7
7
7
Stratix V Device Handbook Volume 1: Overview and Datasheet
Max
20 MHz
13
15
16
Frequency
Unit
ps
ps
ps
2–26