DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 482

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–26
Figure 4–17. Transmitter Clocking Configuration in a PIPE ×4 Configuration
Note to
(1) Serial clock from the ×1 clock lines.
Stratix V Device Handbook Volume 3: Transceivers
Figure
4–17:
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Parallel Clock
Serial Clock
Parallel and Serial Clocks
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
Low-Speed Parallel Clock
High-Speed Serial Clock
Low-Speed Parallel Clock
High-Speed Serial Clock
(1)
(1)
(1)
(1)
(1)
Local Clock Divider
Central Clock Divider
Local Clock Divider
Local Clock Divider
Central Clock Divider
Local Clock Divider
(Master) Transmitter PCS
Transmitter PCS
Transmitter PCS
Transmitter PCS
Transmitter PCS
Transmitter PCS
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Transmitter PMA
Transmitter PMA
Transmitter PMA
Transmitter PMA
Transmitter PMA
Transmitter PMA
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
×6 Clock Lines
PCI Express (PCIe)—Gen1 and Gen2
×1 Clock Lines
May 2011 Altera Corporation