DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 498

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–42
Stratix V Device Handbook Volume 3: Transceivers
In additions to encoding the XGMII data to PCS code groups, per the rules of the
10GBASE-X PCS, the transmitter state diagram performs functions such as converting
Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R|| ordered
sets.
In addition to decoding the PCS code groups to XGMII data, per the rules of the
10GBASE-X PCS, the receive state diagram performs functions such as converting
Sync ||K||, Align ||A||, and Skip ||R|| ordered sets to Idle ||I|| ordered sets.
Synchronization
The word aligner block in the receiver PCS of each of the four XAUI lanes implements
the receiver synchronization state diagram shown in Figure 48-7 of the
IEEE802.3-2008 specification.
The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner
is synchronized to a valid word boundary.
Deskew
The channel aligner block in the receiver PCS implements the receiver deskew state
diagram shown in Figure 48-8 of the IEEE 802.3-2008 specification.
The channel aligner starts the deskew process only after the word aligner block in
each of the four XAUI lanes indicates successful synchronization to a valid word
boundary.
The XAUI PHY IP core provides a status signal to indicate successful lane deskew in
the receiver PCS.
Clock Compensation
The rate match FIFO in the receiver PCS datapath is designed to compensate up to
±100 PPM difference between the remote transmitter and the local receiver. It does so
by inserting and deleting Skip ||R|| columns depending on the PPM difference.
The clock compensation operation begins after:
■
■
The rate match FIFO provides status signals to indicate the insertion and deletion of
the Skip ||R|| column for clock rate compensation.
The word aligner in all four XAUI lanes indicates successful synchronization to a
valid word boundary.
The channel aligner indicates a successful lane deskew.
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
May 2011 Altera Corporation
XAUI