DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 484

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–28
Stratix V Device Handbook Volume 3: Transceivers
f
PIPE ×8 Configuration
Figure 4–19
configuration. Clocking is independent for receiver channels. Clocking and control
signals are bonded only for transmitter channels.
For more information about clocking in Stratix V devices, refer to the
Clocking in Stratix V Devices
shows clocking for PMA and PCS blocks in the ×8 PCIe bonded
chapter.
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
May 2011 Altera Corporation
Transceiver