DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 248

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–4
Table 7–1. DQ/DQS Bus Mode Pins for Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
x4
x8/x9
x16/x18
x32/x36
Notes to
(1) The QVLD pin is not used in the UniPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
(3) If you do not use differential DQS and the group does not have additional signals, the DM pin is supported.
(4) Two x4 DQ/DQS groups are stitched to create a x8/x9 group, so there are a total of 12 pins in this group.
(5) Four x4 DQ/DQS groups are stitched to create a x16/x18 group; so there are a total of 24 pins in this group.
(6) Eight x4 DQ/DQS groups are stitched to create a x32/x36 group, so there are a total of 48 pins in this group.
single-ended DQS signaling. If you use differential or complementary DQS signaling, the maximum number of data per group decreases by
one. This number may vary per DQ/DQS group in a particular device. Check the pin table for the exact number per group. For DDR3 and DDR2
interfaces, the number of pins is further reduced for an interface larger than x8 because you require one DQS pin for each x8/x9 group to form
the x16/x18 and x32/x36 groups.
Mode
(4)
Table
(5)
(6)
7–1:
1
1
DQSn Support
Use differential DQS signaling for DDR2 SDRAM interfaces running at or above
333 MHz.
DQ pins can be bidirectional signals, as in DDR3 and DDR2 SDRAM, and RLDRAM II
common I/O interfaces, or unidirectional signals, as in QDR II+ and QDR II SRAM,
and RLDRAM II separate I/O devices. Connect the unidirectional read-data signals to
Stratix V DQ pins and the unidirectional write-data signals to a different DQ/DQS
group than the read DQ/DQS group. You must assign the write clocks to the
DQS/DQSn pins associated to this write DQ/DQS group. Do not use the CQ/CQn
pin-pair for write clocks.
Using a DQ/DQS group for the write-data signals minimizes output skew, allows
access to the write-leveling circuitry (for DDR3 SDRAM interfaces), and allows
vertical migration. These pins also have access to deskewing circuitry (using
programmable delay chains) that can compensate for delay mismatch between signals
on the bus.
The DQ and DQS pin locations are fixed in the pin table. Memory interface circuitry is
available in every Stratix V I/O bank that does not support transceivers. All the
memory interface pins support the I/O standards required to support DDR3 and
DDR2 SDRAM, QDR II+ and QDR II SRAM, and RLDRAM II devices.
Stratix V devices support DQ and DQS signals with DQ bus modes of x4, x8/x9,
x16/x18, or x32/x36. If any of these pins are not used for memory interfacing, you can
use these pins as user I/Os. In addition, you can use the DQSn or CQn pins that are
not used for clocking as DQ pins.
Table 7–1
DQSn/CQn pin pair.
Yes
Yes
Yes
Yes
lists pin support per DQ/DQS bus mode, including the DQS/CQ and
CQn Support
Yes
Yes
Yes
No
Parity or Data
(Optional)
No
Mask
Yes
Yes
Yes
(3)
Chapter 7: External Memory Interfaces in Stratix V Devices
(Optional)
QVLD
Yes
Yes
Yes
No
(1)
Number of
per Group
Data Pins
16 or 18
32 or 36
Typical
8 or 9
May 2011 Altera Corporation
4
Memory Interface Pin Support
Data Pins per
Number of
Maximum
Group
11
23
47
5
(2)