DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 27

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
Revision History
Revision History
Table 1–13. Revision History
June 2011 Altera Corporation
December 2010
December 2010
January 2011
June 2011
April 2010
May 2011
July 2010
July 2010
May 2010
Date
Table 1–13
Version
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
lists the revision history for this chapter.
Changed 800 MHz to 1,066 MHz for DDR3 in
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Updated Table 1-1.
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Updated Table 1–5
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Updated part numbers in Table 1–1 and Table 1–2
Initial release
For Stratix V GT devices, changed 14.1 Gbps to 12.5 Gbps.
Changed Configuration via PCIe to Configuration via Protocol
Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
Chapter moved to Volume 1.
Added Stratix V GS information.
Updated tables listing device features.
Added device migration information.
Updated 12.5-Gbps transceivers to 14.1-Gbps transceivers
Updated Table 1-1.
Updated Figure 1-2.
Converted to the new template.
Minor text edits.
Updated “Features Summary” on page 1–2
Updated resource counts in Table 1–1 and Table 1–2
Removed “Interlaken PCS Hard IP” and “10G Ethernet Hard IP”
Added “40G and 100G Ethernet Hard IP (Embedded HardCopy Block)” on
page 1–7
Added information about Configuration via PCIe
Added “Partial Reconfiguration” on page 1–12
Added “Ordering Information” on page 1–14
Changes Made
Table 1–8
and in text.
Stratix V Device Handbook
1–21