DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 444

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–28
Figure 2–21. Receiver Datapath Interface Clocking
Stratix V Device Handbook Volume 3: Transceivers
Receiver Datapath Interface Clock
1
(Quartus II Selected Clock)
(User Selected Clock)
rx_clkout/tx_clkout
FPGA Fabric
rx_coreclkin
The Quartus II software does not allow gated clocks or clocks generated in the FPGA
logic to drive the tx_coreclkin ports.
Because the Quartus II software allows you to use external pins, such as dedicated
refclk pins, it has no way of ensuring a 0 PPM difference. You must ensure a 0 PPM
difference.
The receiver datapath interface is comprised of the following:
■
■
This interface is clocked by the receiver datapath interface clock.
receiver datapath interface clocking. The receiver PCS forwards the following clocks
to the FPGA fabric:
■
■
■
All configurations that use the standard PCS channel must have a 0 PPM difference
between the receiver datapath interface clock and the read side clock of the RX phase
compensation FIFO.
Read side of the RX phase compensation FIFO—for configurations that use the
standard PCS channel
Read side of the RX FIFO—for configurations that use the 10G PCS channel
rx_clkout—for each receiver channel in non-bonded configuration when a rate
matcher is not used
tx_clkout—for each receiver channel in non-bonded configuration when a rate
matcher is used
single tx_clkout[0]—for all receiver channels in bonded configuration
rx_clkout
Receiver Data
Receiver Data
Compensation
Phase
FIFO
FIFO
RX
RX
Chapter 2: Transceiver Clocking in Stratix V Devices
Parallel Clock (Recovered Clock)
Parallel Clock (Recovered Clock)
Receiver Standard PCS
FPGA Fabric-Transceiver Interface Clocking
Receiver Data
Receiver Data
Receiver 10G PCS
May 2011 Altera Corporation
Figure 2–21
shows