DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 383

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
PMA Architecture
Figure 1–10. Deserializer Bit Order in Single-Width Mode
Figure 1–11. Transmitter PLL Locations in Stratix V Devices
May 2011 Altera Corporation
Parallel Clock
Transceiver Block
Serial Clock
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
Channel 0
Transmitter PLLs
dataout
datain
0
Figure 1–10
data output of the deserializer block in single-width mode with a 10-bit
deserialization factor. The serial stream (0101111100) is deserialized to a value 10'h17C.
The serial data is assumed to be received LSB to MSB.
The following sections describe the Stratix V transmitter PLLs.
Figure 1–11
TX PCS
TX PCS
TX PCS
RX PCS
TX PCS
TX PCS
RX PCS
TX PCS
RX PCS
RX PCS
RX PCS
RX PCS
0
1
1
shows the transmitter PLL locations.
shows the serial bit order of the deserializer block input and the parallel
1
TX PMA
RX PMA
TX PMA
RX PMA
TX PMA
RX PMA
TX PMA
RX PMA
TX PMA
RX PMA
TX PMA
RX PMA
1
1
0
1
ATX PLL
ATX PLL
0
1
1
0
0
0101111100
0
TX PMA
0
RX PMA
Stratix V Device Handbook Volume 3: Transceivers
0
1
Transmitter PLLs
Channel PLL/
0
Divider
CDR
Clock
1
1010000011
ATX PLL
1–11