DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 8

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–2
Stratix V Device Handbook
Common to all Stratix V family variants are a rich set of high-performance building
blocks, including a redesigned adaptive logic module (ALM), 20 Kbit (M20K)
embedded memory blocks, variable precision DSP blocks, and fractional
phase-locked loops (PLLs). All of these building blocks are interconnected by Altera’s
superior multi-track routing architecture and comprehensive fabric clocking network.
Also common to Stratix V devices is the new Embedded HardCopy Block, which is a
customizable hard IP block that leverages Altera’s unique HardCopy ASIC
capabilities. Use the Embedded HardCopy Block for hardening standard or
logic-intensive functions, such as interface protocols, application-specific functions,
and proprietary custom IP. Incorporating hard IP into the Embedded HardCopy Block
frees up valuable core logic resources and reduces overall system power and cost. The
Embedded HardCopy Blocks in Stratix M20K Memory Blocks devices include a hard
IP instantiation of PCIe Gen 3/2/1 and 40/100GbE.
Chapter 1: Stratix V Device Family Overview
June 2011 Altera Corporation
Stratix V Family Variants