DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 394

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–22
Table 1–6. Synchronization State Machine Modes for Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
Number of valid synchronization code groups or ordered sets received to achieve synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by one
Bit-Slip Mode Word Aligner with an 8-Bit PMA-PCS Interface Configuration
Custom single-width configuration with an 8-bit PMA-PCS interface width allows the
word aligner to be configured in bit-slip mode. In bit-slip mode, the word aligner
operation is controlled by the rx_bitslip bit of the pcs8g_rx_wa_control register. At
every 0-1 transition of the rx_bitslip bit of the pcs8g_rx_control register, the bit-slip
circuitry slips one bit into the received data stream, effectively shifting the word
boundary by one bit. Also in bit-slip mode, the word aligner pcs8g_rx_wa_status
register bit for rx_patterndetect is driven high for one parallel clock cycle when the
received data after bit-slipping matches the 16-bit word alignment pattern
programmed.
You can implement a bit-slip controller in the FPGA fabric that monitors the
rx_parallel_data signal, the rx_patterndetect signal, or both, and controls the
rx_bitslip signal to achieve word alignment.
Automatic Synchronization State Machine Mode Word Aligner with a 10-Bit PMA-PCS
Interface Configuration
Protocols such as PCIe require the receiver PCS logic to implement a synchronization
state machine to provide hysteresis during link synchronization. Each of these
protocols defines a specific number of synchronization code groups that the link must
receive to acquire synchronization and a specific number of erroneous code groups
that it must receive to fall out of synchronization.
In PCIe configurations, the word aligner is in automatic synchronization state
machine mode. It automatically selects the word alignment pattern length and pattern
as specified by each protocol.
Table 1–6
machine parameters are fixed for PCIe configurations as specified by the respective
protocol.
After de-assertion of the reset_rx_digital signal in automatic synchronization state
machine mode, the word aligner starts looking for the word alignment pattern or
synchronization code groups in the received data stream. When the programmed
number of valid synchronization code groups or ordered sets is received, the
rx_syncstatus status bit is driven high to indicate that synchronization is acquired.
The rx_syncstatus status bit is constantly driven high until the programmed number
of erroneous code groups is received without receiving intermediate good groups;
after which rx_syncstatus is driven low. The word aligner indicates loss of
synchronization (rx_syncstatus remains low) until the programmed number of valid
synchronization code groups are received again.
lists the synchronization state machine modes. The synchronization state
Mode
Chapter 1: Transceiver Architecture in Stratix V Devices
May 2011 Altera Corporation
Standard PCS Architecture
PCIe
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16
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