DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 292
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 292 of 530
- Download datasheet (16Mb)
9–12
Figure 9–3. Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. V
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin.
(3) The MSEL pin settings vary for different data width and POR delay. To connect MSEL, refer to
(4)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V
If you use FPP ×8, use DATA[7..0]. If you use FPP ×16, use DATA[15..0]. All devices in the chain must have the same data width.
(MAX II Device or
Microprocessor)
Figure
External Host
ADDR DATA[7..0]
Memory
9–3:
1
Figure 9–3
Stratix V devices receive the same configuration data (single .sof).
In
and complete the configuration and enter user mode at the same time.
To configure FPP multi-device with a single .sof, all Stratix V devices in the chain
must be in the same package and density.
V
Figure
10 kΩ
CCPGM
(1) V
9–3, because both nCE pins are tied to GND, both devices in the chain begin
shows the FPP configuration setup for multiple devices when both
CCPGM
10 kΩ
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
(1)
GND
CONF_DONE
nSTATUS
DATA[31..0]
nCONFIG
DCLK
nCE
Stratix V Device 1
MSEL[4..0]
(4)
nCEO
N.C.
(3)
(2)
Table 9–4 on page
CCPGM
must be high enough to meet the V
GND
Fast Passive Parallel Configuration
9–7.
May 2011 Altera Corporation
nCE
CONF_DONE
nSTATUS
DATA[31..0]
nCONFIG
DCLK
Stratix V Device 2
MSEL[4..0]
(4)
nCEO
CCPGM
.
N.C.
(3)
IH
(2)
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX230N](/photos/28/41/284156/dk-dev-4sgx230n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: