mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1031

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

42.3.5 I2C Data I/O register (I2Cx_D)
Addresses: I2C0_D is FFFF_81C0h base + 4h offset = FFFF_81C4h
Freescale Semiconductor, Inc.
RXAK
DATA
IICIF
Field
Reset
Field
Read
7–0
Write
1
0
Bit
I2C1_D is FFFF_81D0h base + 4h offset = FFFF_81D4h
I2C2_D is FFFF_81E0h base + 4h offset = FFFF_81E4h
I2C3_D is FFFF_81F0h base + 4h offset = FFFF_81F4h
0
1
Interrupt flag
This bit sets when an interrupt is pending. This bit must be cleared by software or by writing a 1 to it in the
interrupt routine. One of the following events can set this bit:
0
1
Receive acknowledge
0
1
Data
In master transmit mode, when data is written to this register, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte
of data.
NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the
In slave mode, the same functions are available after an address match occurs.
7
0
• One byte transfer including ACK/NACK bit completes if FACK = 0
• One byte transfer excluding ACK/NACK bit completes if FACK = 1. An ACK or NACK is sent on the
• Match of slave address to calling address including primary slave address, range slave address,
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
Slave receive, master writing to slave
Slave transmit, master reading from slave
No interrupt pending
Interrupt pending
Acknowledge signal was received after the completion of one byte of data transmission on the bus
No acknowledge signal detected
bus by writing 0 or 1 to TXAK after this bit is set in receive mode
alert response address, second slave address, or general call address.
Data register to prevent an inadvertent initiation of a master receive data transfer.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
I2Cx_S field descriptions (continued)
I2Cx_D field descriptions
0
5
Preliminary
0
4
Description
Description
DATA
0
3
Chapter 42 Inter-Integrated Circuit (I2C)
0
2
0
1
0
0
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