mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 917

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
SPTEF
MODF
SPMF
Field
6
5
4
assuming another SPI message is not received. When the receive DMA request is enabled (RXDMAE is
1), SPRF is automatically cleared when the DMA transfer for the receive DMA request is completed (RX
DMA Done is asserted).
0
1
SPI match flag
SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the MH:ML
registers. To clear the flag, read SPMF when it is set and then write a 1 to it.
0
1
SPI transmit buffer empty flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty
flag (when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This bit is set when
the transmit data buffer is empty. When the transmit DMA request is disabled (TXDMAE is 0), SPTEF is
cleared by reading the S register with SPTEF set and then writing a data value to the transmit buffer at
DH:DL. The S register must be read with SPTEF set to 1 before writing data to the DH:DL register;
otherwise, the DH:DL write is ignored. When the transmit DMA request is enabled (TXDMAE is 1), SPTEF
is automatically cleared when the DMA transfer for the transmit DMA request is completed (TX DMA
Done is asserted). SPTEF is automatically set when all data from the transmit buffer transfers into the
transmit shift register. For an idle SPI, data written to DH:DL is transferred to the shifter almost
immediately so that SPTEF is set within two bus cycles, allowing a second set of data to be queued into
the transmit buffer. After completion of the transfer of the data in the shift register, the queued data from
the transmit buffer automatically moves to the shifter, and SPTEF is set to indicate that room exists for
new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set
and no data moves from the buffer to the shifter.
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): If a transfer does not
stop, the last data that was transmitted is sent out again.
When the FIFO is supported and enabled (FIFOMODE is 1): This bit provides the status of the FIFO
rather than of an 8-bit or a 16-bit buffer. This bit is set when the the transmit FIFO is empty. When the
transmit DMA request is disabled (TXDMAE is 0), SPTEF is cleared by writing a data value to the transmit
FIFO at DH:DL. When the transmit DMA request is enabled (TXDMAE is 1), SPTEF is automatically
cleared when the DMA transfer for the transmit DMA request is completed (TX DMA Done is asserted).
SPTEF is automatically set when all data from the transmit FIFO transfers into the transmit shift register.
For an idle SPI, data written to the DH:DL register is transferred to the shifter almost immediately, so that
SPTEF is set within two bus cycles. A second write of data to the DH:DL register clears this SPTEF flag.
After completion of the transfer of the data in the shift register, the queued data from the transmit FIFO
automatically moves to the shifter, and SPTEF will be set only when all data written to the transmit FIFO
has been transfered to the shifter. If no new data is waiting in the transmit FIFO, SPTEF simply remains
set and no data moves from the buffer to the shifter.
0
1
Master mode fault flag
No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is
not full (when FIFOMODE is 1)
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full
(when FIFOMODE is 1)
Value in the receive data buffer does not match the value in the MH:ML registers
Value in the receive data buffer matches the value in the MH:ML registers
SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when
FIFOMODE is 1)
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when
FIFOMODE is 1)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_S field descriptions (continued)
Table continues on the next page...
Preliminary
Description
Chapter 38 Serial Peripheral Interface (SPI)
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