mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 268

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Processor Exceptions
1. Effective address of (d16,PC) not supported
2. Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is
11.3.4.7 Branch Instruction Execution Times
268
MULU.L
MULU.
Opcod
Opcode
BRA
BSR
JMP
RTE
RTS
JSR
performed (MACSR[7:4] equals 1---, -11-, --11)
W
e
Opcode
Bcc
<EA>
<ea>
<ea>
<ea>y, Dx
<ea>y, Dx
The execution times for moving the contents of the Racc,
Raccext[01,23], MACSR, or Rmask into a destination location
<ea>x shown in this table represent the best-case scenario when
the store instruction is executed and there are no load or
M{S}AC instructions in the EMAC execution pipeline. In
general, these store operations require only a single cycle for
execution, but if they are preceded immediately by a load,
MAC, or MSAC instruction, the depth of the EMAC pipeline is
exposed and the execution time is three cycles.
<EA>
Table 11-30. EMAC Instruction Execution Times (continued)
Table 11-31. General Branch Instruction Execution Times
Rn
—
—
—
—
—
—
Table 11-32. Bcc Instruction Execution Times
Forward
3 (0/0)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Taken
3 (0/0)
3 (0/1)
3 (0/0)
3 (0/0)
(An)
—
—
—
—
Rn
5 (1/0)
5 (1/0)
5 (1/0)
(An)+
(2/0)
(An)
—
—
—
—
7
Preliminary
Not Taken
Forward
Note
1(0/0)
5 (1/0)
5 (1/0)
(An)+
-(An)
—
—
—
—
—
—
Effective Address
Effective Address
5 (1/0)
5 (1/0)
-(An)
(d
(d
2 (0/1)
3 (0/1)
3 (0/0)
3 (0/1)
16
16
—
—
,An)
,PC)
(d16,An)
5 (1/0)
5 (1/0)
Backward
2 (0/0)
Taken
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
4 (0/0)
4 (0/1)
—
—
—
—
(d8,An,
Xn*SF)
6 (1/0)
Freescale Semiconductor, Inc.
—
xxx.wl
3 (0/0)
3 (0/1)
5 (1/0)
xxx.wl
—
—
—
—
—
Not Taken
Backward
3 (0/0)
3 (0/0)
#xxx
#xxx
—
—
—
—
—
—
—