mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 761

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

35.2.1 Detailed signal descriptions
35.3 Memory map and register definition
Freescale Semiconductor, Inc.
FFFF_84CC Low Power Timer Counter Register (LPTMR0_CNR)
FFFF_84C0 Low Power Timer Control Status Register (LPTMR0_CSR)
FFFF_84C4 Low Power Timer Prescale Register (LPTMR0_PSR)
FFFF_84C8 Low Power Timer Compare Register (LPTMR0_CMR)
FFFF_84D0 Low Power Timer Control Status Register (LPTMR1_CSR)
FFFF_84D4 Low Power Timer Prescale Register (LPTMR1_PSR)
Absolute
address
(hex)
LPTMR_ALTn
Signal
All LPTMR registers are reset by the Chip POR not VLLS reset
type and by POR Only, which triggers Chip POR not VLLS.
Each register's displayed reset value represents this subset of
reset types. LPTMR registers are unaffected by other reset
types. For more information about the types of reset on this
chip, refer to the the Reset details.
Table 35-2. LPTMR interface-detailed signal descriptions
I/O
I
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Pulse counter input.
The LPTMR can select one of the input pins to be used in pulse counter mode.
Register name
State meaning
Table continues on the next page...
LPTMRx memory map
Timing
Preliminary
NOTE
Assertion-If configured for pulse counter mode with active
high input then assertion causes the LPTMR counter
register to increment.
Negation-If configured for pulse counter mode with active
low input then negation cause the LPTMR counter
register to increment.
Assertion or negation may occur at any time; input may
assert asynchronously to the bus clock.
Description
(in bits)
Width
32
32
32
32
32
32
Chapter 35 Low Power Timer (LPTMR)
Access
R/W
R/W
R/W
R/W
R/W
R
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
Section/
35.3.1/
35.3.2/
35.3.3/
35.3.4/
35.3.1/
35.3.2/
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