mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 654

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional description
29.4.3 Hardware trigger and channel selects
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT,
that is enabled when the ADTRG bit is set and a hardware trigger select event
(ADHWTSn) has occurred. This source is not available on all MCUs. Refer to the Chip
Configuration chapter for information on the ADHWT source and the ADHWTSn
configurations specific to this MCU.
When a ADHWT source is available and hardware trigger is enabled (ADTRG=1), a
conversion is initiated on the rising edge of ADHWT after a hardware trigger select event
(ADHWTSn) has occurred. If a conversion is in progress when a rising edge of a trigger
occurs, the rising edge is ignored. In continuous convert configuration, only the initial
rising edge to launch continuous conversions is observed, and until conversion gets
aborted the ADC continues to do conversions on the same ADC status and control
register that initiated the conversion. The hardware trigger function operates in
conjunction with any of the conversion modes and configurations.
The hardware trigger select event (ADHWTSn) must be set prior to the receipt of the
ADHWT signal. If these conditions are not met, the converter may ignore the trigger or
use the incorrect configuration. If a hardware trigger select event gets asserted during a
conversion, it must stay asserted until the end of current conversion and remain set until
the receipt of the ADHWT signal to trigger a new conversion. The channel and status
fields selected for the conversion depend on the active trigger select signal (ADHWTSA
active selects SC1A; ADHWTSn active selects SC1n).
When the conversion is completed, the result is placed in the data registers associated
with the ADHWTSn received (ADHWTSA active selects RA register; ADHWTSn active
selects Rn register). The conversion complete flag associated with the ADHWTSn
received (the COCO bit in SC1n register) is then set and an interrupt is generated if the
respective conversion complete interrupt has been enabled (AIEN=1).
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Asserting more than one hardware trigger select signal
(ADHWTSn) at the same time results in unknown results. To
avoid this, select only one hardware trigger select signal
(ADHWTSn) prior to the next intended conversion.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Note
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