mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 355

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

ColdFire processors inhibit interrupt sampling during the first instruction of all exception
handlers. This allows any handler to effectively disable interrupts, if necessary, by raising
the interrupt mask level contained in the status register as the first instruction in the ISR.
In addition, the V1 instruction set architecture (ISA_C) includes an instruction
(STLDSR) that stores the current interrupt mask level and loads a value into the SR. This
instruction is specifically intended for use as the first instruction of an interrupt service
routine that services multiple interrupt requests with different interrupt levels. For more
details see the ColdFire Family Programmer's Reference Manual. A MOVE-to-SR
instruction also performs a similar function.
To emulate the HCS08's 1-level IRQ nesting mechanisms, the ColdFire implementation
enables interrupts by clearing SR[I] (typically when using RTE to return to a process) and
disables interrupts upon entering every interrupt service routine by one of three methods:
15.7.2 Using INTC_PL6P{7,6} Registers
The INTC Programmable Level 6, Priority {7,6} registers (INTC_PL6P{7,6}) provide
the ability to dynamically alter the request level and priority of two IRQs. Specifically,
these registers provide the ability to reassign two IRQs to be the highest level 6
(maskable) requests. Consider the following example.
Suppose the system operation desires to remap the receive and transmit interrupt requests
of a serial communication device (SCI1) as the highest two maskable interrupts. The
default assignments for the SCI1 transmit and receive interrupts are:
To remap these two requests, the INTC_PL6P{7,6} registers are programmed with the
desired interrupt source number:
Freescale Semiconductor, Inc.
1. Execution of STLDSR #0x2700 as the first instruction of an ISR.
2. Execution of MOVE.w #0x2700,SR as the first instruction of an ISR.
3. Static assertion of CPUCR[IME] that forces the processor to load SR[I] with seven
• sci1_rx = interrupt source 13 (0Dh) = vector 77 = level 24, priority 6
• sci1_tx = interrupt source 14 (0Eh) = vector 78 = level 24, priority 5
automatically upon the occurrence of an interrupt exception. Because this method
removes the need to execute multi-cycle instructions of #1 or #2, this approach
improves system performance.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 15 Interrupt Controller (INTC)
355