mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 801

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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may affect all channels selectively since FAULTM[1:0] and FAULTEN control bits are
defined for each pair of channels. Since there are several FAULTj inputs, maximum of 4
for the FTM module, each one of these inputs is activated by the FAULTjEN bit in the
FLTCTRL register.
37.2.4 PHA — FTM Quadrature Decoder Phase A Input
The quadrature decoder phase A input is used when the quadrature decoder mode is
selected (if the quadrature decoder feature is supported). The phase A input signal is one
of the signals that control the FTM counter increment or decrement in the quadrature
decoder mode
37.2.5 PHB — FTM Quadrature Decoder Phase B Input
The quadrature decoder phase B input is used when the quadrature decoder mode is
selected (if the quadrature decoder feature is supported). The phase B input signal is one
of the signals that control the FTM counter increment or decrement in the quadrature
decoder mode
37.3 Memory Map and Register Definition
This section provides a detailed description of all FTM registers.
37.3.1 Module Memory Map
This section presents a high-level summary of the FTM registers and how they are
mapped.
The FTM memory map can be split into two sets of registers. The first set has the original
TPM registers.
The second set has the FTM specific registers. Any second set registers (or bits within
these registers) that are used by an unavailable function in the FTM configuration remain
in the memory map and in the reset value, so they have no active function.
Freescale Semiconductor, Inc.
Do not write to the FTM specific registers (second set registers)
when FTMEN = 0.
(Quadrature Decoder
(Quadrature Decoder
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Mode).
Mode).
Preliminary
Note
Chapter 37 FlexTimer (FTM)
801

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