mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 815

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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37.3.11 Counter Initial Value High (FTMx_CNTINH)
The Counter Initial Value registers contain the high and low bytes of the initial value for
the FTM counter.
Writing to either byte latches the value into a buffer. The register is updated with the
value of their write buffer.
When BDM is active, the write coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active, even if one or both
bytes of the counter initial value register are written while BDM is active. Any write to
the counter initial value registers bypasses the buffer latches and writes directly to the
counter initial value register while BDM is active.
The first time that the FTM clock is selected (first write to change the CLKS bits to a
non-zero value), FTM counter starts with the value 0x0000. To avoid this behavior,
before the first write to select the FTM clock, write the new value to the Counter Initial
Value registers and then initialize the FTM counter (write any value to CNT).
Addresses: FTM0_CNTINH is FFFF_8440h base + 1Dh offset = FFFF_845Dh
Freescale Semiconductor, Inc.
INIT_H
Reset
Field
Read
7–0
Write
Bit
FTM1_CNTINH is FFFF_8480h base + 1Dh offset = FFFF_849Dh
Counter Initial Value High Byte
7
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FTMx_CNTINH field descriptions
0
5
Preliminary
0
4
INIT_H
Description
0
3
0
2
Chapter 37 FlexTimer (FTM)
0
1
0
0
815

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