mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 148

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Clock distribution
5.2.3 Architecture
Various clocks are generated by dividing the MCGOUTCLK clock:
In addition to the MCGOUTCLK clock dividers, there are other clock dividers to
generate:
5.2.4 Clock divider requirements
The flash memory's LPBOOT bit of the option byte loaded to the FTFL_FOPT register
controls the reset value of the core clock, system clock, and bus clock dividers. For a
definition of LPBOOT and other bits of the option byte, refer to
148
0
1
USB clock (USB_CLK) 48 MHz
SAI/I
• Core clock — Clocks the ColdFire V1 core
• System clock — Clocks the crossbar switch and bus masters directly connected to
• Bus clock — Clocks the bus slaves and peripheral (excluding memories)
• an accurate 48 MHz clock source for the USB OTG Controller
• the SAI/ I
the crossbar. In addition, this clock is used for UART0 and UART1.
Clock name
2
(SAI_CLK)
S master clock
LPBOOT
2
S master clock
Up to 50 MHz
0xF
0x0
Run mode
clock frequency
SIM_CLKDIV0[OUTDI
Table 5-2. Device Clock Summary (continued)
Table 5-3. LPBOOT's effect on clock dividers
MCF51JF128 Reference Manual, Rev. 2, 03/2011
V]
N/A
Up to 2 MHz
Divide by 16
Divide by 1
VLPR mode
clock frequency
Core/system clock
Preliminary
MCGPLLCLK or
MCGFLLCLK with
fractional clock divider,
or
USB_CLKIN
System clock,
MCGPLLCLK, with
fractional clock divider,
ERCLK1 or ERCLK2
I2S_MCLK
Divide by 32
Divide by 2
Clock source
Bus clock
FOPT boot
Freescale Semiconductor, Inc.
USB OTG is disabled
SAI/I
Low power boot
Fast clock boot
Clock is disabled
when…
2
options.
S is disabled
Description