mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 918

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Register Definition
918
TNEAREF
RNFULLF
TXFULLF
RFIFOEF
Field
3
2
1
0
MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some
other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when
MSTR is 1, MODFEN is 1, and SSOE is 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1 and then writing to the SPI control register 1 (C1).
0
1
Receive FIFO nearly full flag
This flag is set when more than three 16-bit words or six 8-bit bytes of data remain in the receive FIFO,
provided C3[4] is 0, or when more than two 16-bit words or four 8-bit bytes of data remain in the receive
FIFO, provided C3[4] is 1. It has no function if FIFOMODE is not present or is 0.
0
1
Transmit FIFO nearly empty flag
This flag is set when only one 16-bit word or two 8-bit bytes of data remain in the transmit FIFO, provided
C3[5] is 0, or when only two 16-bit words or four 8-bit bytes of data remain in the transmit FIFO, provided
C3[5] is 1. If FIFOMODE is not enabled, ignore this bit.
NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register
0
1
Transmit FIFO full flag
This bit indicates the status of the transmit FIFO when FIFOMODE is enabled. This flag is set when there
are 8 bytes in the transmit FIFO. If FIFOMODE is not enabled, ignore this bit.
0
1
SPI read FIFO empty flag
This bit indicates the status of the read FIFO when FIFOMODE is enabled. If FIFOMODE is not enabled,
ignore this bit.
NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register
0
1
No mode fault error
Mode fault error detected
Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1)
Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32
bits (when C3[4] is 1)
Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1)
remaining to transmit
Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when
C3[5] is 1) remaining to transmit
Transmit FIFO has less than 8 bytes
Transmit FIFO has 8 bytes of data
Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will
empty the read FIFO.
Read FIFO is empty.
and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this
type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If this
type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this
type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If this
type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_S field descriptions (continued)
Preliminary
Description
Freescale Semiconductor, Inc.