mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 480

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Modes of operation
22.2 Modes of operation
The FMC operates only when the chip accesses the program flash memory or
FlexMemory. In terms of chip power modes:
22.3 External signal description
The FMC has no external (off-chip) signals.
22.4 Memory map and register descriptions
The ColdFire CPU's programming model provides control and configuration of the flash
controller's speculation and cache functions with bits in the CPU Control Register
(CPUCR). For details, see the description of the
480
• Interface between the device and the 32-bit program flash memory and FlexMemory:
• Acceleration of data transfer from the program flash memory to the device:
• The FMC operates only in run and wait modes, including VLPR and VLPW modes.
• For any power mode where the program flash memory or FlexMemory cannot be
accessed, the FMC is disabled.
• 8-bit, 16-bit, and 32-bit read operations to nonvolatile memory (flash and
• 8-bit, 16-bit, and 32-bit read and write operations to the FlexNVM and
• Consecutive read accesses (such as 0x0,0x4) to program flash memory return the
• 32-bit prefetch speculation buffer for program flash accesses for crossbar switch
• 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen
FlexNVM used as data flash memory).
FlexRAM used as EEPROM.
second read data with no wait states when the buffer or cache is enabled. The
memory returns 32 bits via the 32-bit bus access.
master 0 (V1 ColdFire CPU) with controls for instruction/data access
32-bit entries with invalidation control
Program the Flash Memory Controller's configuration and
control settings only while the Flash Memory Controller is idle.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
NOTE
CPUCR
register.
Freescale Semiconductor, Inc.