mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1280

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
The address breakpoint registers are accessible in supervisor mode using the WDEBUG
instruction and through the BDM port using the WRITE_DREG command using values
shown in BDM Command Set Descriptions.
1280
R
W
ABHR
Reset
ABLR
Reset
R
W
ABHR
Reset
ABLR
Reset
• Inside the range bound by ABLR and ABHR inclusive
• Outside that same range
DRc: 0x0C (ABHR)
Address
Address
31–0
31–0
Field
Field
0x0D (ABLR)
31
–
0
15
–
0
Version 1 ColdFire core devices implement a 24-bit, 16 MB
address map. When programming these registers with a 32-bit
address, the upper byte should be zero-filled when referencing
the flash, RAM, and RGPIO regions, and set to 0xFF when
referencing any of the slave peripheral devices.
30
–
0
14
–
0
Table 50-30. Address Breakpoint Registers (ABLR, ABHR)
Low address
Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
specific addresses are programmed into ABLR.
High address
Holds the 32-bit address marking the upper bound of the address breakpoint range.
Description
Description
29
–
0
13
–
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
–
0
12
–
0
Table 50-32. ABHR Field Descriptions
Table 50-31. ABLR Field Descriptions
27
–
0
11
–
0
26
–
0
10
–
0
25
–
0
9
–
0
Preliminary
NOTE
24
–
0
8
–
0
Address
Address
23
–
0
7
–
0
22
–
0
6
–
0
21
–
0
5
–
0
20
–
0
4
–
0
Freescale Semiconductor, Inc.
Access: Supervisor write-only
19
3
–
0
–
0
18
–
0
2
–
0
BDM write-only
17
–
0
1
–
0
16
–
0
0
–
0