mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 135

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

3.11.2.1 Instantiation Information
The maximum total number of GPIO pins for general purpose is 48 in the 64-pin
packages. Smaller packages have fewer available GPIO pins. For details, refer to package
pinout information in
GPIO pins are configured in 8-pin ports. The peripheral bus interface for the EGPIO
operates at the bus clock.
Only two EGPIO ports have the digital filter feature: Port B and Port C. The other ports
do not have this feature.
3.11.2.2 EGPIO registers
Every EGPIO port has two banks of registers. Each bank has a separate base address
shared by all ports' registers in that bank.
Freescale Semiconductor, Inc.
1. One bank consists of registers for general port control. For details about these
2. The other bank's registers control functions such as configurable slew rate, drive
System memory map
Power management
Signal multiplexing
Full description
registers, refer to
strength, pullups/pulldowns, and passive input filters. For details about these
registers, refer to
Clocking
Topic
Table 3-56. Reference links to related information
Port mux control
Related module
Port
Parallel Input/Output
Signal
EGPIO
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Control.
Figure 3-45. EGPIO configuration
Multiplexing.
EGPIO controller
Preliminary
Peripheral
bridge
Control.
Register
access
Parallel Input/Output Control
System memory map
Power management
Module signals
Signal multiplexing
Clock distribution
Reference
Chapter 3 Chip Configuration
135