mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 618

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
27.4.2 True Random Number Generator (TRNG)
The TRNG is comprised of two entropy sources each providing a single bit of output.
Concatenated together, these two output bits are expected to provide one bit of entropy
every 100 clock cycles. In addition to generating entropy, the TRNG also performs
several statistical tests on its output. The pass/fail status of these tests are reflected in
RNG_ESR.
27.4.3 Resets
There are two ways to reset the RNGB: power-on/hardware reset and software reset. The
software reset is functionally equivalent to the power-on/hardware reset. The power-on/
hardware reset is asynchronous. Software reset is performed by setting the
RNG_CMD[SR] bit. These are summarized in the table below.
27.4.3.1 Power-on/Hardware Reset
Asserting the ipg_hard_async_reset_b signal sets all interface registers to their default
state and puts the state machine into the IDLE mode.
27.4.3.2 Software Reset
The software reset is functionally equivalent to the hardware reset, but allows the RNGB
to be fully reset by writing to the SW_RST bit (bit-6) in the RNGB Command Register.
This bit is self-resetting. A software reset may be performed at any time.
618
Hardware
Software
Reset
ipg_hard_async_reset_b
RNG_CMD[SR]
Source
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 27-8. Reset Summary
minimum 1-cycle
Characteristics
asynchronous,
Preliminary
Active-high
Active-low,
All interface registers
All interface registers
and puts RNGB into
and puts RNGB into
Internally resets:
the IDLE state
the IDLE state
Freescale Semiconductor, Inc.
Affect on External
Signal:
—
—