mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1148

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Reset
Memory Map and Registers
44.3.7 SAI Transmit Data Register (I2Sx_TDR)
Addresses: I2S0_TDR is FFFF_8200h base + 20h offset = FFFF_8220h
44.3.8 SAI Transmit FIFO Register (I2Sx_TFR)
The MSB of the read pointer and write pointer is used to distinguish between FIFO full
and empty conditions. If the read and write pointers are identical then the FIFO is empty.
If the read and write pointers are identical except for the MSB then the FIFO is full.
Addresses: I2S0_TFR is FFFF_8200h base + 40h offset = FFFF_8240h
1148
Bit
Bit
W
W
R
R
TDR[31:0]
Reserved
Reserved
31
31
0
0
31–19
18–16
31–0
WFP
Field
Field
Field
7–0
30
30
0
0
29
29
0
0
28
28
0
0
This read-only bitfield is reserved and always has the value zero.
Transmit data register
Writes to this register when the transmit data channel is enabled and not full will push the data written into
the transmit FIFO. Otherwise, writes to this register are ignored.
This read-only bitfield is reserved and always has the value zero.
Write FIFO pointer
27
27
0
0
26
26
0
0
25
25
0
0
0
24
24
0
0
I2Sx_TCR5 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
23
0
0
22
22
0
0
21
21
0
I2Sx_TDR field descriptions
0
I2Sx_TFR field descriptions
Table continues on the next page...
20
20
0
0
19
19
0
0
18
18
0
0
Preliminary
WFP
17
17
0
0
TDR[31:0]
16
16
0
0
0
15
15
0
0
Description
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
RFP
0
0
1
1
0
0
0
0