mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 934

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low,
but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the
first bit of data from the shifter onto the MOSI output of the master and the MISO output
of the slave. The next SPSCK edge causes both the master and the slave to sample the
data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge,
the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and
MISO outputs of the master and slave, respectively. When CPHA = 1, the slave's SS
input is not required to go to its inactive high level between transfers.
The following figure shows the clock formats when SPIMODE = 0 and CPHA = 0. At
the top of the figure, the eight bit times are shown for reference with bit 1 starting as the
slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first
and LSB first lines show the order of SPI data bits depending on the setting in LSBFE.
Both variations of SPSCK polarity are shown, but only one of these waveforms applies
for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform
applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform
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(MISO OR MOSI)
(MASTER OUT)
(REFERENCE)
(SLAVE OUT)
SAMPLE IN
MSB FIRST
(CPOL = 1)
BIT TIME #
(CPOL = 0)
LSB FIRST
(MASTER)
(SLAVE)
SS OUT
SPSCK
SPSCK
SS IN
MOSI
MISO
Figure 38-38. SPI Clock Formats (CPHA = 1)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
BIT 7
BIT 0
1
BIT 6
BIT 1
2
Preliminary
...
...
...
BIT 2
BIT 5
6
BIT 1
BIT 6
7
Freescale Semiconductor, Inc.
BIT 0
BIT 7
8