mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 926

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
38.4.3 Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear.
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• SPSCK
• MISO, MOSI pin
• SS pin
In slave mode, SPSCK is the SPI clock input from the master.
In slave mode, the function of the serial data output pin (MISO) and serial data input
pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register
2.
• If MODFEN and SSOE bit are set, the SS pin is configured as slave select
output. The SS output becomes low during each transmission and is high when
the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is
configured as input for detecting mode fault error. If the SS input becomes low
this indicates a mode fault error where another master tries to drive the MOSI
and SPSCK lines. In this case, the SPI immediately switches to slave mode by
clearing the MSTR bit and also disables the slave output buffer MISO (or SISO
in bidirectional mode). As a result, all outputs are disabled, and SPSCK, MOSI
and MISO are inputs. If a transmission is in progress when the mode fault
occurs, the transmission is aborted and the SPI is forced into idle state. This
mode fault error also sets the mode fault (MODF) flag in the SPI Status Register
(SPIx_S). If the SPI interrupt enable bit (SPIE) is set when the MODF flag gets
set, then an SPI interrupt sequence is also requested. When a write to the SPI
Data Register in the master occurs, there is a half SPSCK-cycle delay. After the
delay, SPSCK is started within the master. The rest of the transfer operation
differs slightly, depending on the clock format specified by the SPI clock phase
bit, CPHA, in SPI Control Register 1 (see
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN,
SPC0, BIDIROE with SPC0 set, SPIMODE, FIFOMODE,
SPPR2-SPPR0 and SPR3-SPR0 in master mode abort a
transmission in progress and force the SPI into idle state. The
remote slave cannot detect this, therefore the master has to
ensure that the remote slave is set back to idle state.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Note
SPI Clock
Formats).
Freescale Semiconductor, Inc.