mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1192

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
46.3.4 Port Slew Rate Enable Register (PCTLx_SRE)
Addresses: PCTLA_SRE is FFFF_9200h base + 3h offset = FFFF_9203h
46.3.5 Port Passive Filter Enable Register (PCTLx_PFE)
The PFE register enables control of the input low-pass filter on the pad. The filter is
enabled by setting the bit corresponding to a given pin. When set high, a low pass filter
(10 MHz to 30 MHz bandwidth) is enabled in the logic input path. When set low, the
filter is bypassed.
The filter is enabled during and after reset by setting the associated PTPFE bit. The filter
is disabled through software control by clearing the associated PTPFE bit.
1192
PTSRE[7:0]
PTDS[7:0]
Field
Reset
Field
7–0
Read
7–0
Write
Bit
PCTLB_SRE is FFFF_9210h base + 3h offset = FFFF_9213h
PCTLC_SRE is FFFF_9220h base + 3h offset = FFFF_9223h
PCTLD_SRE is FFFF_9230h base + 3h offset = FFFF_9233h
PCTLE_SRE is FFFF_9240h base + 3h offset = FFFF_9243h
PCTLF_SRE is FFFF_9250h base + 3h offset = FFFF_9253h
Port output drive strength control bits
Each of these control bits selects between low and high output drive for the associated port pin. For port
pins that are configured as inputs, these bits have no effect.
0
1
Port output slow rate enable bits
Each of these control bits determines whether the output slew rate control is enabled for the associated
port pin. For port pins that are not configured as outputs, these bits have no effect.
0
1
7
0
Low output drive strength selected.
High output drive strength selected.
Slew rate control disabled.
Slew rate control enabled.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
PCTLx_SRE field descriptions
PCTLx_DS field descriptions
0
5
Preliminary
0
4
PTSRE[7:0]
Description
Description
0
3
0
2
Freescale Semiconductor, Inc.
0
1
0
0